Development of an Application-Specific Instruction-set Processor for efficient and fast QR-Decomposition in MIMO Detection of WiFi (802.11ax) and 5G MODEM Systems
The Open Source Processor, RISC-V (32-bits, Integer) Processor, adds a VLIW structure to enable efficient and fast Vector Load/Store, Complex Vector Inner Product, Complex Vector Scaling, and more.
It aims to develop application-specific instruction-set processors that can efficiently and quickly perform QR-decomposition used for MIMO detection of WiFi (802.11ax) MODEM System.
In the case of RISC-V, an open source processor set as a reference in this work, there is no support for Vector Load/Store, Vector/Matrix Arithmetic, and Complex Number, which has the disadvantage of being slow when performing the functions.
In the case of a simple operation-only block that supports the above functions, it shows strength in terms of speed and area, but it is difficult to cope with changes in parameters such as the number of Antenna or changes in Algorithm.
Therefore, we want to combine the advantages of the processor and the dedicated block by adding VLIW structural design, dedicated instruction, and functional unit to the RISC-V processor.
Not only MIMO Detection, but also a single processor capable of advancing the WiFi system, including Chanel Estimation and LDPC Decoding blocks. In addition to WiFi, it can be utilized for accelerators requiring Matrix/Vector operations, such as CNNs.
The combined processors functioning as Channel Estimation (FFT/IFFT), Soft Demapper, and LDPC Decoder can be configured to take full responsibility for the operation of Wi-Fi modems on one processor.